FIG. 1 is an illustration of a general purpose computer 20. The computer 20 includes a central processing unit (CPU) 22. The CPU 22 executes instructions of a computer program. Each instruction is located at a memory address. Similarly, the data associated with an instruction is located at a memory address. The CPU 22 accesses a specified memory address to fetch the instruction or data stored there.
Most CPUs include an on-board memory called a cache. The cache stores a set of memory addresses and the instructions or data associated with the memory addresses. If a specified address is not in the internal, or L1 cache, then the CPU 22 looks for the specified address in an external cache, also called an L2 cache 24. The external cache is typically implemented using Static Random Access Memories (SRAMs). Standard SRAMs are simply storage devices. Thus, they are operated with a separate circuit known as an external cache controller 26.
If the address is not in the external cache 24 (a cache miss), then the external cache 24 requests access to a system bus 28. When the system bus 28 becomes available, the external cache 24 is allowed to route its address request to the primary memory 30. The primary memory 30 is typically implemented using Dynamic Random Access Memories (DRAMs). As in the case of SRAMs, DRAMs are simply memory devices. Thus, they are operated with a separate circuit known as an external memory controller 32.
The data output from the primary memory 30 is applied to the system bus 28. It is then stored in the external cache 24 and is passed to the CPU 22 for processing. The processing described in reference to FIG. 1 must be performed for every address request. Indeed, if the address request is not found in the primary memory 30, similar processing is performed by an input/output controller 34 associated with a secondary memory 36.
As shown in FIG. 1, there are additional devices connected to the system bus 28. For example, FIG. 1 illustrates an input/output controller 38 operating as an interface between a graphics device 40 and the system bus 28. In addition, the figure illustrates an input/output controller 42 operating as an interface between a network connection circuit 44 and the system bus 28.
The multiple connections to the system bus 28 result in a relatively large amount of traffic. It would be desirable to remove memory transactions from the system bus 28 in order to reduce traffic on the system bus 28. It is known to remove memory transactions from the system bus 28 by using a separate memory bus for external cache 24 and a separate memory bus for primary memory 30. This approach results in a relatively large number of CPU package pins. It is important to reduce the number of CPU package pins. Thus, it would be highly desirable to reduce the traffic on the system bus without increasing the number of CPU package pins. In addition, it would be desirable to eliminate the need for the external logic associated with external cache and primary memories.